A semiconductor device for controlling power has a structure where a plurality of transistors having different fabrication factors, such as impurity doping concentration in an active region, thickness of a gate insulation layer and the like, according to the desired characteristics are integrated in one substrate. The semiconductor device for controlling power uses many expanded drain MOS (EDMOS) transistors. It is well known that when a semiconductor device for controlling power is designed, a threshold voltage VT should be secured while maintaining a breakdown voltage BV desired for the transistors.
EDMOS transistors are commonly used in a high voltage semiconductor device and have higher input impedance than that of bipolar transistors. Accordingly, a power gain of an EDMOS transistor may be comparatively large, and a gate driving circuit may be more simply implemented. Also, because the EDMOS transistor is a unipolar device, delay does not occur or is prevented, where the delay occurs due to accumulation or recombination of minority carriers during an extended turn-off.
FIGS. 1A to 1C illustrate a conventional semiconductor device for controlling power. FIG. 1A is a plan view. FIG. 1B is a cross-sectional view of the conventional semiconductor device for controlling power shown in FIG. 1A taken along the line X-X′. FIG. 1C is a cross-sectional view of the conventional semiconductor device for controlling power shown in FIG. 1A taken along the line Y-Y′. In the drawings, a semiconductor device for controlling power including EDMOS transistors each having an N channel is illustrated as an example.
Referring to FIGS. 1A to 1C, the conventional semiconductor device for controlling power will be described hereafter. EDMOS transistors are formed in the respective regions of a substrate 11 including a first region and a second region, where the second region has a relatively lower operation voltage than the first region. Herein, each of the EDMOS transistors includes a P-type first deep well 12A or 12B and an N-type second deep well 13A or 13B formed over the substrate 11, an active region 14A or 14B, a gate electrode 21, a gate insulation layers 20A or 20B, an N-type source region 17, a P-type pickup region 18, a P-type first impurity region 19, an N-type drain region 15 and an N-type second impurity region 16.
The active regions 14A and 14B are defined by a device isolation layer 22 formed over a substrate 11, and have a structure where the P-type first deep wells 12A are junctioned respectively with 12B and the N-type second deep wells 13A and 13B. The gate electrode 21 crosses both the P-type first deep well 12A or 12B and the N-type second deep well 13A or 13B over the substrate 11. The gate insulation layers 20A and 20B are interposed between the gate electrode 21 and the substrate 11. The N-type source region 17 is formed over the P-type first deep wells 12A and 12B adjacent one end of the gate electrode 21. The P-type pickup region 18 is formed over the P-type first deep wells 12A and 12B to be spaced apart from the N-type source region 17 by a predetermined distance. The P-type first impurity region 19 is formed over the P-type first deep wells 12A and 12B to surround the P-type pickup region 18. The N-type drain region 15 is formed over the N-type second deep wells 13A and 13B to be spaced apart from, and on the opposite side from the N-type source region 17 of, the gate electrode 21. The N-type second impurity region 16 is formed over the N-type second deep wells 13A and 13B to surround the N-type drain region 15.
Herein, since the gate insulation layer 20A and the gate insulation layer 20B are simultaneously formed in a first region and a second region, respectively, during the fabrication of the semiconductor device for controlling power, the gate insulation layers 20A and 20B formed in the first and second regions respectively have substantially the same thickness (i.e., T1=T2) in order to simplify the process for fabricating a semiconductor device for controlling power. Therefore, an EDMOS transistor formed in the first region, which has a greater operation voltage than an EDMOS transistor formed in the second region, can secure a sufficient breakdown voltage only when the impurity doping concentrations of the P-type first deep well 12A and the N-type second deep well 13A formed in the first region is lower than the impurity doping concentrations of the P-type first deep well 12B and the N-type second deep well 13B.
When the impurity doping concentrations of the P-type first deep well 12A and the N-type second deep well 13A formed in the first region is lower in the conventional semiconductor device for controlling power, the threshold voltage values of the EDMOS transistor formed in the first region may decrease below the desired threshold voltage level due to the low impurity doping concentrations of the P-type first deep well 12A and the N-type second deep well 13A. To solve this problem, additional impurity may be implanted into the channel region C of the EDMOS transistor formed in the first region (see the portion marked ‘A’ in FIG. 1B) through an additional mask process or an ion implantation process so as to secure the threshold voltage. When such method is used, the number of the procedural steps of the process for fabricating a semiconductor device for controlling power is increased, resulting in an increase in the production costs and time. Herein, the channel region C of the EDMOS transistor may be defined as the surface area of the substrate 11 where the gate electrode 21 overlaps with the P-type first deep well 12A in the active regions 14A or with the P-type first deep well 12B in the active regions 14B. That is, the channel region C of the EDMOS transistor in the first region may be defined as the surface area of the substrate 11 corresponding to the area of overlap between the P-type first deep wells 12A of the active regions 14A and the gate electrode 21. It should be noted that the channel region C may have a width that is narrower than the entire width of overlap between the gate electrode 21 and the P-type first deep well 12A over the entire depth into the substrate 11. That is, when, for example, as shown in FIG. 1C, a device isolation layer 22 is formed to create the sidewalls B of the P-type first deep well 12A so as to result in a narrower P-type first deep well 12A at the surface of the substrate 11, it is the overlapping area of the substrate surface that defines the channel region C.
The device isolation layer 22 is typically formed through a shallow trench isolation (STI) process. During the processing or doping of the P-type first deep well 12A, an impurity, e.g., boron, may be impregnated to the device isolation layer 22 in a region (see a portion marked with ‘H’ in FIG. 1A) adjacent to both the P-type first deep well 12A and the device isolation layer 22 in a lower portion of the gate electrode 21 in a direction of channel width (which is Y-Y′ direction), so that the doping concentration of the channel region C adjacent to the device isolation layer 22 may be decreased locally.
When the doping concentration of the channel region C near the device isolation layer 22 is locally decreased in the direction of channel length (which is X-X′ direction), a value of a predetermined threshold voltage level is varied. Also, a hump effect can occur, and thus, operational characteristics of the semiconductor device may be deteriorated.
FIG. 1D illustrates a cross-sectional view of another conventional semiconductor device for controlling power. Again, a semiconductor device for controlling power formed of EDMOS transistors each having an N channel is illustrated as an example.
Referring to FIG. 1D, a method for fabricating the conventional semiconductor device for controlling power will be described hereafter. P-type first deep wells 12A and 12B and N-type second deep wells 13A and 13B are formed performing an impurity ion implantation onto a substrate 11 including a first region and a second region. Thereafter, a device isolation layer 22 is formed to define active regions 14A and 14B having a structure where the P-type first deep wells 12A and 12B and the N-type second deep wells 13A and 13B are junctioned with each other, respectively.
Thereafter, P-type first impurity regions 19A and 19B are formed by performing an impurity ion implantation onto a portion of the substrate 11 with the P-type first deep wells 12A and 12B formed therein, and N-type second impurity regions 16A and 16B are formed by performing an impurity ion implantation onto a portion of the substrate 11 with the N-type second deep wells 13A and 13B formed therein.
Thereafter, a mask pattern is formed to open a channel region C over the substrate 11, and a threshold voltage control layer 24A (24B) are formed over the first and second regions by using the mask pattern as an implantation barrier and performing an ion implantation process.
Thereafter, gate insulation layers 20A and 20B are formed over the substrate 11. Herein, the thickness of the gate insulation layer 20A formed in the first region is different from the thickness of the gate insulation layer 20B formed in the second region (T1≠T2).
Thereafter, a gate conductive layer is formed over the substrate 11, and the gate conductive layer and the gate insulation layers 20A and 20B are sequentially etched to thereby provide the gate insulation layers 20A and 20B and the gate electrode 21 in the first region and the second region. Thereafter, a gate is formed to cross both the P-type first deep wells 12A and 12B and the N-type second deep wells 13A and 13B.
Thereafter, P-type pickup regions 18A and 18B are formed over the P-type first impurity regions 19A and 19B, and N-type source regions 17A and 17B are formed over the P-type first deep wells 12A and 12B. N-type drain regions 15A and 15B are formed over the N-type second impurity regions 16A and 16B.
A semiconductor device for controlling power fabricated through the above-described process can have a high operation voltage. To secure a breakdown voltage characteristic, the conventional semiconductor device for controlling power is formed to have a low impurity doping concentration in the P-type first deep wells 12A and 12B and the N-type second deep wells 13A and 13B. When the impurity doping concentrations of the P-type first deep wells 12A and 12B and the N-type second deep wells 13A and 13B are brought down to secure the breakdown voltage characteristic, a threshold voltage level of a corresponding transistor is drastically decreased, which may be programmatic. Also, where the gate insulation layers 20A and 20B are provided thinner with the P-type first deep wells 12A and 12B and the N-type second deep wells 13A and 13B formed to have a low impurity doping concentration, the threshold voltage level is further decreased.
To address this, the conventional method provides the threshold voltage control layers 24A and 24B in the channel region C of the substrate 11 through a mask process and an ion implantation process. Herein, the channel region C of an EDMOS transistor may be defined as a surface area of the substrate 11 where the gate electrodes 21 and the P-type first deep wells 12A and 12B are overlapped.
However, since the threshold voltage control layers 24A and 24B should be formed to have different characteristics, such as the impurity conductive type, the kind of impurity, the amount of ion to be implanted and so forth, according each transistor formed in each region in consideration of the impurity doping concentrations of the P-type first deep wells 12A and 12B and the N-type second deep wells 13A and 13B and the thicknesses of the gate insulation layers 20A and 20B, the number of procedural steps increases as well as the production unit cost and production time.